The present invention covers a method of burst data transfer incorporated in the bus interfacing unit of a microprocessor known as the Intel 80486.RTM. microprocessor, frequently referred to as the 486.RTM. processor. The 486 microprocessor is an improved version of the Intel 80386.RTM. microprocessor (commonly referred to as the 386.RTM. processor) which includes a 32-bit internal data bus; details of the bus for the 386 processor are described in numerous publications. The 386 processor also includes an on-chip memory management unit. This unit provides addressing to, for example, a cache memory, DRAMs, mass storage, etc. The processor described in this application further includes an on-chip cache memory as well as an on-chip floating point unit. (Intel, 80486, 486, 80386 and 386 are trademarks of Intel Corporation.)
For bus requests that require more than a single data cycle, many microprocessors can accept burst cycles instead of normal cycles. A burst cycle transfers multiple bytes of data across the bus during one long memory cycle. For example, a transfer of a 128-bit data item across a 32-bit bus would normally occur in four groups, each group containing 4 bytes. The initial address (e.g., the first byte) is used by the processor to compute the remaining addresses for the subsequent data bytes.
While the concept of burst cycle transfers is well-known in the field, there remains considerable debate over the most efficient way of ordering the transferred data. The burst order refers to the choice of addresses for the sequence of multiple data cycles. One obvious choice employed in the past has been to order the data sequentially starting from zero. For the example given above, a sequential burst order from zero would first transfer the 32-bit doubleword (also called a dword) residing at address zero. The next transfers would be to the dwords at addresses 4, 8 and 12, in order.
Another past approach was to initially transfer the dword that the user wanted to operate on immediately; then increment the address, wrapping around the cache line. This approach is known as the "wrap-around burst (nibble mode)" transfer method. Assuming that the user wants to access dword 3 (dword 3 representing the 32-bit item stored at address 12, e.g., dwords 0-3 corresponding to addresses 0,4,8 and 12, respectively), the received burst order would be 12, 0, 4, 8. In other words, the desired data item is transferred first and the remaining items are transferred in circular sequential order. Whereas the dword residing at address 12 is referenced immediately, the remaining dwords, e.g., 0,4,8, are needed to fill the cache line even though they are not initially referenced.
The wrap-around burst method has an important advantage over the burst from zero method in its ability to first reference the 32-bit dword containing the data referenced by the internal CPU, then completing the burst with the rest of the cache line to fill in the cache. However, a significant drawback is that the wrap-around burst method cannot be used to couple a 32-bit CPU to a 64-bit memory bus in an optimum manner.
The present invention represents an improvement over these prior methods; providing a fast and efficient method of transferring data to an aligned region of main memory. The new burst order permits access to the relevant data first, then filling in the remaining part of the cache line. Importantly, the new burst order supports the connection of a 32-bit CPU to a 64-bit memory bus. In addition to supplying a high-bandwidth transfer for filling cache lines, the burst order of the present invention also has advantages in 486 CPU-based systems, and for use in future systems with wider busses and longer line sizes. These advantages are described later in the application.
Other prior art known to Applicant are the bus signals associated with the Multibus-including the Multibus II (Multibus is a trademark of Intel Corporation). Additionally, other prior art known to applicant is shown in copending application, Ser. No. 006,353, filed Jan. 14, 1987, entitled "High Speed Local Bus and Data Transfer Method", and in copending application, Ser. No. 227,078, filed Aug. 1, 1988, entitled "Microprocessor Bus interface Unit", both of which are assigned to the assignee of the present invention. Further, the following prior art patents are known to applicant: U.S. Pat. Nos. 4,570,220; 4,447,878; 4,442,484; 4,315,308; and, 4,315,310.